1. Field of the Invention
The present invention relates to a ring buffer circuit in which pointers may be circulated within a predetermined address area to perform read and write operations, and to a control circuit for the ring buffer circuit. In particular, the present invention relates to a ring buffer circuit in which read and write operations may be asynchronously performed using a dual port memory, and to a control circuit for the ring buffer circuit.
2. Description of the Related Art
It is generally important for a first-in first-out (FIFO) type data buffer device (hereinafter, referred to as FIFO buffer) to output a signal indicating an internal state to an external circuit (hereinafter, referred to as internal state signal), to prevent writing in a state in which a storage region is full (hereinafter, referred to as full state) or reading in an empty state in which the reading of all write data from the storage region is completed (hereinafter, referred to as empty state). There is a case where the internal state signal to be output may indicate not only the full state or the empty state but also a remaining amount state of the FIFO buffer.
In a general first-in first-out operation for the FIFO buffer, a read and write memory having a predetermined address area is controlled by using a write pointer (WP) indicating a data write address and a read pointer (RP) indicating a data read address. The write pointer (WP) and the read pointer (RP) are used for circulation access to the predetermined address area of the read and write memory. Therefore, the read and write memory is used as a so-called ring buffer, to thereby realize the function of the FIFO buffer. Addresses of the write pointer (WP) and the read pointer (RP) are updated for each writing and reading. After writing and reading in a final address are completed, each of the addresses is returned to a first address to continue writing and reading.
In general, in a case of a synchronous ring buffer circuit in which writing and reading are performed in synchronization with a common clock signal, the addresses of the write pointer (WP) and the read pointer (RP) are updated in synchronization with the common clock signal, and hence the internal state signal is also generated in synchronization with the common clock signal.
In contrast to this, in a case of an asynchronous ring buffer circuit in which data writing and data reading are performed for access, based on separate clock signals, the addresses of the write pointer (WP) and the read pointer (RP) are updated in synchronization with the different clock signals. In this case, the clock signal used for reading is different from the clock signal used for writing, and hence the respective pointers may not be directly referred to. Therefore, it is necessary to synchronize the pointers, based on the clock signal on the referring side of the pointers.
Each of the pointers has a width of a plurality of bits. Therefore, when the pointers are simply synchronized based on a reference destination clock during a metastable state in which a source pointer is changing, a correct pointer value may not be referred to.
In general, in order to solve such a problem, a counter in which the plurality of bit widths are not simultaneously changed during one clock period, that is, a hamming distance is 1 may be used to avoid an erroneous operation at the time of synchronization. In particular, when the ring buffer has an n-bit address space (address space of n-th power of two), a gray code counter which may include n-bits is used. When the gray code counter is provided as the write pointer (WP) or the read pointer (RP), the number of elements becomes slightly larger than in a case of a normal binary counter, but an output value of the gray code counter may be used as an address of the read and write memory without any change.
As described above, it is necessary to generate the internal state signal indicating the internal state of the ring buffer, which is sent to the outside. For example, in the case of each of the full state and the empty state, the write pointer (WP) is equal in value to the read pointer (RP). Therefore, when the write pointer (WP) is simply compared with the read pointer (RP), the full state and the empty state may not distinguished from each other. Thus, there is a method of generating an internal state signal for distinguishing the full state and the empty state from each other, based on additional bits inverted when each of the pointers is returned from a final address to zero (hereinafter, referred to as additional bits).
This method is described in FIG. 2 of JP 2005-148904 A. As illustrated in FIG. 2 of JP 2005-148904 A, an additional bit (one bit) is provided for each of a ten-bit write pointer and a ten-bit read pointer, and thus eleven-bit information is used to generate the internal state signal. The lower ten bits are used for each of the pointers.
The following analysis is provided according to the present invention. When the method of distinguishing the full state and the empty state from each other based on the additional bits described in JP 2005-148904 A is to be applied to the asynchronous ring buffer described above, there is the following problem. When the write pointer (WP) and the read pointer (RP) change, the additional bits simultaneously change. Therefore, even in a case where the write pointer (WP) and the read pointer (RP) are gray-encoded, when the additional bits are included, a plurality of bits simultaneously change, and hence the erroneous operation may not be avoided.
Further, if the entire write pointer (WP) or read pointer (RP) which includes the additional bit is gray-encoded, the number of gray code bits becomes lager than the number of bits required for addressing to the read and write memory. Therefore, the addressing to the read and write memory may not be realized directly based on the gray code bits.